Memories such as Static Random Access Memories (SRAM) and Dynamic Random Access Memories (DRAM) are widely used in high-speed applications due to their improved performance.
A typical memory array includes word-lines and bit-lines connected to the memory cells in the memory array. The bit lines may include one bit-line or a pair of bit-lines (with often-inversed phases) connected to each column of the memory cells. Before a read operation is started to read the value stored in a memory cell, the respective bit-line is pre-charged, for example, to 0.6V. In the read operation, the voltage on the pre-charged bit-line may be updated in accordance with the value stored in the SRAM cell. By detecting the voltage on the bit-line, the value stored in the memory cell is thus determined.
In a conventional bit-line pre-charge scheme, each of the bit-lines in a memory array is connected to a common charge line through a switch. The common charge line is further connected to a bias voltage that the bit-lines are to be charged to. A charge transistor connects the common charge line to the bias voltage. The charge transistor is typically an NMOS transistor. When a bit-line needs to be pre-charged, the switch of the respective bit-line and the charge transistor are both turned on, so that the bias voltage is connected to the respective bit-line, and the bit-line is pre-charged by the voltage.
When the bit-line capacitance is high, for example, when the respective bit-line is long due to the high number of memory cells connected to this bit-line, the pre-charge may take long time to finish, and hence the operation speed of the memory array is adversely affected. Particularly, the charging speed is increasingly reduced with the proceeding of the pre-charge process. This is caused by the increasing reduction in the gate-to-source voltage of the charge transistor. When the bit-line has been charged to, for example, 80 percent or 90 percent of the target bit-line voltage, the gate-to-source voltage of the charge transistor is reduced to a very low level, and the current flowing through the charge transistor, hence the pre-charging speed, becomes very low. Although a large charge transistor may be used to accelerate the pre-charge process, the required chip area is also increased.